Strided access allows a vector architecture to pipelined access to non-sequential memory locations provided that there is no bank conflict.

Using memory banks improves vector performance by increasing bandwidth.

Vector mask registers can parallelize code even when if conditionals introduce dependencies.

Using a register to define the length of a vector can improve vector performance.

Vector performance can be improved by increasing the number of lanes if enough parallel function units are available.

A discussion about vector architecture, memory system, instructions and execution time.

An article on how a single CPU handles multiple threads. Three different (coarse, fine and simultaneous) are discussed.

An example walkthrough of a set of loop instructions undergoing Tomasulo’s algorithm. Each stage of the lifecycle is explained in detail.

This article discusses the lifecycle (issue, execute, write, commit) of an instruction following Tomasulo’s Algorithm.

A short explanation of the role of Common Data Bus.