Coherence cache misses can occur due to word (true) or block (false) sharing.
Continue readingMSI Protocol – Example
Worked out example of changes to cache contents under MSI protocol.
Continue readingMSI Protocol
MSI Protocol explained through state diagrams. Challenges and extensions mentioned.
Continue readingWrite Invalidate and Write Broadcast Protocol
Comparison of write invalidate versus write broadcast cache coherence protocol.
Continue readingCache Coherence Protocols
Cache coherence protocol is implemented by tracking the state of any sharing of a data block.
Continue readingCache Coherence and Consistency
A coherent and consistency memory model ensures that all processors have access to the same data.
Continue readingMultiprocessing
Multicore processors, their communication models and some example classes.
Continue readingOpenCL vs CUDA terminology
Terminology differences between OpenCL and CUDA.
Continue readingOpenCL – Memory Model
Hierarchy of OpenCL memory model and how data is allocated/shared.
Continue readingOpenCL – Kernel Space
Visualizing OpenCL kernel space, dimensions and indexing.
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