The Beard Sage

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True Sharing, False Sharing and Ping-Ponging

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Coherence cache misses can occur due to word (true) or block (false) sharing.

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MSI Protocol – Example

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Worked out example of changes to cache contents under MSI protocol.

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MSI Protocol

posted in Computer Architecture on May 3, 2020 by TheBeard 1 Comment

MSI Protocol explained through state diagrams. Challenges and extensions mentioned.

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Write Invalidate and Write Broadcast Protocol

posted in Computer Architecture on May 3, 2020 by TheBeard 2 Comments

Comparison of write invalidate versus write broadcast cache coherence protocol.

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Cache Coherence Protocols

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Cache coherence protocol is implemented by tracking the state of any sharing of a data block.

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Cache Coherence and Consistency

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

A coherent and consistency memory model ensures that all processors have access to the same data.

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Multiprocessing

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Multicore processors, their communication models and some example classes.

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OpenCL vs CUDA terminology

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Terminology differences between OpenCL and CUDA.

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OpenCL – Memory Model

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Hierarchy of OpenCL memory model and how data is allocated/shared.

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OpenCL – Kernel Space

posted in Computer Architecture on May 3, 2020 by TheBeard 0 Comments

Visualizing OpenCL kernel space, dimensions and indexing.

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