Understanding DRAM data sheet specifications and memory timings

This article explores how to read data sheet specifications and memory timings and use that to solve a few example questions.


A DIMM specification will mention the capacity. For example, the Micron 2GB SDRAM DIMM MT9KSF25672PZ has a combined DRAM capacity of 2GB. This DIMM will contain individual DRAM chips called modules. If the DIMM supports ECC error there will be one extra DRAM module for this. Unless mentioned, it is assumed that all the DRAM chips belong to a single rank. The width of the data bus of this rank is partitioned equally across all the DRAM chips. For example, if the data width is 64 bits and say there are 8 chips (excluding ECC), then each chip will contribute 8 bits.


A DRAM Chip is also referred to as the base device. The specification will mention the capacity. For example, the MT41K256M8 2Gb DDR3 SDRAM chip has a capacity of 2Gb. The number of DRAM chips required to fit the DIMM will be 2GB/2Gb = 8

Memory Timings

Memory timings describe the performance of DRAM using a set of parameters in units of clock cycles. They are written as numbers separated with dashes

    \begin{equation*} t_\text{CL} - t_\text{RCD} - t_\text{RP} = 11 - 11 - 11 \end{equation*}

When translating memory timings into actual latency, it is important to note that they are in units of bus clock cycles, which for double data rate (DDR) memory is half the speed of the commonly quoted transfer rate.

For example, DDR3-1600 memory has a 800MHz CPU clock frequency, which yields a 1.25ns CPU clock cycle. With this 1.25ns CPU clock, the memory timings in nanoseconds are

    \begin{equation*} t_\text{CL} - t_\text{RCD} - t_\text{RP} = (11 - 11 - 11) * 1.25 = 13.75 - 13.75 - 13.75 \end{equation*}

DRAM Configuration

A DRAM configuration will specify the capacity of one cell of data, the number of columns, the number of rows and the number of banks. For example, 32K rows \times 1K columns \times 8 bits \times 8 banks gives a total of 2Gb. This is the same as the capacity of a single DRAM chip.

Q1. Number of DDR3 SDRAM chips

8 SDRAM chips are needed to satisfy the capacity of the DIMM. One extra chip is needed for ECC error detection. Thus a total of 9 SDRAM chips are present on the DIMM.

Q2. Longest latency to read 64 bytes of data

The longest latency will occur when the data is not already present in the Row Buffer. In this case a Precharge command has to be issued first. This is followed by a Row Access command. Once the row is loaded in the Row Buffer a Column Read command is issued. This process takes t_\text{RP} - t_\text{RCD} + t_\text{CL} time.

    \begin{equation*} t_\text{RP} + t_\text{RCD} + t_\text{CL} = 13.75 + 13.75 + 13.75 = 41.25\text{ns} \end{equation*}

In each clock cycle, 8 bits of data can be read from each of the 8 DRAM Chips. This sums up to 64 bits of data per DRAM read rate. To read 64 bytes of data will thus require 8 DRAM read rate cycles. Since the DRAM date read rate is 1600 MHz, this equates to

    \begin{equation*} 8 \text{ DRAM read cycles} = \frac{8}{1600\text{M}} = 5\text{ns} \end{equation*}

Thus, the total time will be 41.25 + 5 = 46.25ns.

Q3. How many rows must be refreshed per REFRESH command

It is required to refresh every cell within a 64ms interval. The refresh rate is 7.8125\mu sec.

The Refresh command reads and restores the data in DRAM devices. The memory controller sends a single refresh command to the DRAM device, and the DRAM device goes through a row cycle for a fixed number of rows (say x) in all of the banks in the DRAM device. The same set of rows is sent to all banks to be refreshed concurrently.

Thus, x rows are refreshed per REFRESH command. There are 32K rows in a DRAM chip. So, the number of REFRESH commands that have to be issued is given by

    \begin{equation*} \frac{32 \times 1024}{x} \end{equation*}

A REFRESH command is issued every 7.8125\mu sec. So, the time taken for to issue the above number of REFRESH commands is given by

    \begin{equation*} \frac{32 \times 1024}{x} \times 7.8125 \mu \end{equation*}

This should equate to 64ms. Thus

    \begin{align*} \frac{32 \times 1024}{x} \times 7.8125 \mu = 0.064 \implies x = \frac{32 \times 1024 \times 7.8125 \mu}{0.064} = 4 \end{align*}

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