Throughput of an instruction pipeline is determined by how often an instruction exits the pipeline.
The number of stages in a pipeline or the number of stages between two instructions during execution.
Program Counter (PC)
The register containing the address of the instruction in the program being executed.
A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.
A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer- visible registers or memory. Forwarding paths are valid only if the destination stage is later in time than the source stage.
A stall initiated in order to resolve a hazard.
To discard instructions in a pipeline, usually due to an unexpected event.
Branch Target Address
The address specified in a branch, which becomes the new program counter (PC) if the branch is taken. In the MIPS architecture the branch target is given by the sum of the offset field of the instruction and the address of the instruction following the branch.
A branch where the branch condition is satisfied and the program counter (PC) becomes the branch target. All unconditional jumps are taken branches.
Branch Not Taken
A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch.
A method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.
An unscheduled event that disrupts program execution; used to detect overflow.
An exception that comes from outside of the processor.
The organization of the processor, including the major functional units, their interconnection, and control.
The instruction set of visible registers of a processor; for example, in MIPS, these are the 32 integer and 16 floating-point registers.