The three types of Cache Misses – Compulsory, Capacity and Conflict are discussed. Few strategies to reduce these misses and their tradeoffs are discussed.

This article lists various simple and advanced Cache Optimizations to reduce Hit Time. Hardware based optimizations are discussed.

A hierarchical explanation of various DRAM related nomenclature with detailed figures and example configurations.

This article lists various simple and advanced Cache Optimizations to reduce Miss Rate. Both hardware and software based optimizations are discussed.

A clear understanding of various Cache organization concepts and the math behind it. Different address mapping schemes are discussed with descriptive images and detailed examples.

An intuitive explanation of Write Allocate. All combinations of Write Back and Write Through schemes with Write and No-Write Allocate are discussed.

This article discusses an advanced cache optimization to reduce miss penalty by allowing the processor to resume execution as soon as the requested word within a cache block is available.

A 4-block cache is visualized as the nodes of a tree to approximate LRU. The different configurations are discussed in detail to point out the recency of blocks and how the configuration changes upon cache reference.

A list of definitions of Cache related terminology with some examples.

The advantages and disadvantages of two write policies – write-through and write-back are discussed. The use of a write buffer is also mentioned.