A discussion about various types of compiler and hardware dependencies and the hazards they generate.

An exploration of various static and dynamic Branch Prediction related concepts.

Loop unrolling is a compiler optimization technique to increase instruction level parallelism. The decisions behind this technique and its limitations are discussed.

A brief explanation of Speculation and how to handle exceptions both from the hardware and software side.

A list of definitions of Pipelining/Parallelism related terminology.

This article lists various simple and advanced Cache Optimizations to reduce Miss Penalty. Both hardware and software based optimizations are discussed.

This article explores how to read data sheet specifications and memory timings and use that to solve a few example questions.

The many factors that define a Cache Architecture is presented as a tabular framework for quick reference.

Write merging combines writes to consecutive memory addresses into a single buffer entry. This article explores at this process in depth through detailed example figures.

A step by step approach to understanding the commands issued to a DRAM to access data. Figures and examples included.